In prior art MOS technology, the gain is severely limited by the inherently low transconductance, g.sub.m, of the MOS transistor. The transconductance in a MOST (MOS transistor) is proportional to the ratio Z/L (the channel width (Z) to the channel length (L) of the device). Any attempt at increasing the gain by increasing the channel width (Z) of the device, or by cascading gain stages, results in large area consumption and increase in parasitic capacitances. Decreasing the channel length (L) of the MOS transistor to increase the transconductance has its limitations in the fact that it causes a degradation (increase) in output conductance g.sub.o of the device and thus causes a degradation of the voltage gain which is proportional to the ratio g.sub.m /g.sub.o. Therefore, attempts to overcome the low transconductance by modifying the Z/L ratio are not suitable.
A MOS transistor, as shown in FIG. 1a, may be represented by a small signal model which consists of a current generator g.sub.m v.sub.i, (where v.sub.i is the input gate voltage) and an output conductance g.sub.o. (FIG. 1b).
An inverting gain stage comprising a driver transistor 10 and a load transistor 12 is shown in its most general form in FIG. 2. The driver transistor current generator (g.sub.md v.sub.i) is a function of the input signal v.sub.i only, while the current generator [g.sub.m1 (k.sub.a v.sub.i +k.sub.b v.sub.o)] in the load transistor can be affected by both the input and/or the output signals. The small signal gain of the generalized inverter of FIG. 2 is given by ##EQU1## where g.sub.load is the effective conductance of the load transistor and is given by g.sub.load =g.sub.o1 +k.sub.b g.sub.m1 The constants k.sub.a and k.sub.b can have a value of one or zero depending on the type of inverter. Examples of which are shown in FIGS. 3(a), (b) and (c).
The principal disadvantage of the above-mentioned gain stage is that the maximum gain obtainable is low due to the low value of g.sub.m and the high value of g.sub.o, particularly in the case of short channel MOS transistors. The maximum gain is given by ##EQU2## and is achieved using the CMOS stage shown in FIG. 3a.
An object of the present invention is to provide a higher gain amplifying stage than is achievable with the prior art.
A higher gain stage is accordingly provided which utilizes a negative conductance to reduce the total load conductance of the amplifying stage. The new arrangement allows positive feedback to be delivered to the input of the load, which causes K.sub.b 0 and effectively reduces g.sub.load. g.sub.load can be reduced from positive to negative values by decreasing the attenuation of a positive feedback stage A. A negative g.sub.load can then be used to cancel the positive output conductance of the driver g.sub.od, as well as the resistance of the load R.sub.L. This can result in a near infinite voltage gain. In addition, the presence of positive feedback introduces phase lead which may have useful implications in amplifier design.
The high gain amplifier of the subject application is particularly adaptable to implementation in amplifiers, comparators and oscillators. An important advantage of this invention is that the high gain is provided by a single stage only; this allows easier composition of the amplifier and also frees the input and the output stages from the requirements of providing gain. Those stages can then be designed to optimise other input/output specifications such as input offset, dynamic range and current driving capability.